1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technique suitably applicable to a resin-encapsulated LSI package (TSOP: Thin Small Outline Package) having an LOC (Lead On Chip) structure of a large scale integrated circuit.
2. Description of the Related Art
Demands on information and communication apparatuses are increasing yearly in the recent information age. Of these information and communication apparatuses, portable information apparatuses particularly increasingly demanded, such as a camcorder, a PHS (Personal Handyphone System), and a notebook personal computer, tend to be made entirely smaller and thinner to improve the portability. Accordingly, LSI packages incorporated into these apparatuses are naturally required to be made smaller and thinner.
Meanwhile, as the large scale integration of semiconductor elements advances, the chip area of a semiconductor gradually increases. Consequently, it becomes difficult to accommodate semiconductor elements in a package with required dimensions in a packaging method by which a chip is die-bonded to the die pad of a lead frame.
To eliminate this difficulty, LOC TSOPs such as described in Japanese Patent Laid-Open No. 4-291950 have been proposed and put into practical use.
FIG. 13A is a plan view schematically showing a representative TSOP having an LOC sturcture before resin encapsulation. FIG. 13B is a sectional view showing the representative TSOP after resin encapsulation taken along a line D-D' in FIG. 13A. The structure of this TSOP will be described below in order of its manufacturing steps. First, one surface of insulating tape 3 is bonded to the lower surfaces of inner leads 2 in a lead frame 10 comprising the inner leads 2, outer leads 12, tiebars 13 and a base portion 14. The other surface of the insulating tape 3 bonded to the lead frame 10 is bonded to a predetermined position of the surface of a semiconductor chip 4 in a central portion of which bonding pads 1 are formed. The bonding pads 1 on the semiconductor chip 4 are electrically connected to the inner leads 2 by bonding wires 5. Subsequently, the semiconductor chip 4 is entirely encapsulated with an encapsulating resin 7 by transfer molding. The tiebars 13 and the base portion 14 in the lead frame 10 are cut and the leads are formed into a desired shape, thereby completing the TSOP.
The TSOP thus formed can be made small because a dimension in particularly the lateral direction can be reduced as compared with a package in which wire bonding is performed to inner leads arranged outside a semiconductor chip.
It is predicted that demands on thin reliable TSOPs having a thickness of 1 mm or less will increase in the future with the spread of IC cards and the like. A TSOP having the conventional LOC structure as described above can be made thinner by the following techniques:
(1) lowering the loop of a bonding wire (lowering the locus of a bonding wire from the surface of a semiconductor chip); PA1 (2) reducing the thickness of a semiconductor chip; PA1 (3) reducing the thickness of a frame; PA1 (4) reducing the thickness of an insulating tape, or PA1 (5) reducing the thickness of an encapsulating resin.
When a package is thinned by any of the above techniques, however, a TSOP having the conventional LOC structure poses the following problems.
When a package is thinned by (1) lowering the loop of a bonding wire, variations in the loop height increase the probability of contact of a bonding wire with an inner lead or a bus bar. This increases the possibility of production of defective devices.
When a package is thinned by (2) reducing the thickness of a semiconductor chip, it is necessary to increase the polishing amount of the rear surface of a semiconductor wafer in a back grinding step before the wafer is cut into chips. However, it is inevitable to further increase the wafer diameter in the future for the purpose of improving the productivity. As the diameter is increased, the warp of a wafer resulting from the stress of various films deposited on the wafer in the process of manufacturing a semiconductor circuit increases. When the rear surface of a wafer having this large warp is polished, the semiconductor chip thickness in the center of the wafer becomes different from that in the edge of the wafer. To prevent this, it is necessary to perform polishing after the rear surface of the wafer is forcibly flattened by vacuum suction or the like. However, this method is unpreferable because the wafer can be broken. Also, it is unpreferable to perform back grinding after semiconductor chips are cut out because this extends the period of the manufacturing process.
When a package is thinned by (3) reducing the thickness of a frame, the strength of a lead frame material decreases. This increases the possibility of a break of the frame when outer leads are formed into a predetermined shape or the package is incorporated into an electronic apparatus, resulting in low reliability.
When a package is thinned by (4) reducing the thickness of an insulating tape, the capacitance between a lead frame and a semiconductor chip increase excessively or the resistance against an external stress to the semiconductor chip decreases. In the worst case, the semiconductor chip cracks. This deteriorates the electrical characteristics and the reliability.
When a package is thinned by (5) reducing the thickness of an encapsulating resin, the thickness of the package has its limit of thinning because a certain encapsulating resin thickness is necessary on the upper surface of a semiconductor chip to ensure a region for passing bonding wires. Therefore, it is necessary to reduce the encapsulating resin thickness on the lower surface (rear surface) of the chip. On the other hand, the warp of a package results from the difference between the shrinkage forces (ratios) of encapsulating resins on the two sides of a semiconductor chip, and this shrinkage force difference depends upon the volume ratio of the encapsulating resins. Accordingly, when the thickness of the encapsulating resin on the lower surface of the chip is reduced, the encapsulating resin volume on the lower surface of the chip becomes smaller than that on the upper surface, and this warps the package.